1. Field of the Invention
The present invention relates generally to semiconductor devices and more particularly to MOSFET array cell contacts.
2. Discussion of the Prior Art
FIG. 1 shows the layout of a conventional channel implant programming read only memory (ROM) cell array. There is, for example, one cell PR1 defined in the rectangular area AB.times.AD inside corner points A, B, C and D, having a shared (active) source region CS1, polycrystalline silicon (or polycide) gate or word line WL1, and a shared (active) drain region CD with a shared drain contact CC to an overlying metal bit line BL.
FIG. 2A is a cross-section through the FIG. 1 cells along line 2A--2A from lower shared source region CS1 lengthwise along channel CHN1, across shared drain contact CC, and along channel CHN2 to upper shared source region CS2. Channel conductivities may be programmed by implanting Boron at a high energy (around 180 Kev) and dosage (around 1E13) through the polysilicon gates into the channel regions CHN1, CHN2. Cell PR1's vertical dimensions AD, BC extend from the middle of shared source region CS1 to the middle of shared drain contact CC. The vertical dimensions depend upon, and to be scaled down require reducing at least one of, the drain contact CC size, the drain contact CC spacing from gate WL1, the channel CHN1 length (i.e., word line WL1 width) and the shared source region CS1 height.
FIG. 2B is a cross-section along line 2B--2B through FIG. 1 cells PR1 and PR2. Cell PR1's horizontal dimension AB, DC extend from the center of the gap left of metal bit line BL to the center of the gap right of the bit line. The horizontal dimensions depend upon, and to be scaled down require reducing, each of the active drain region vertical column-to-column spacing, drain contact CC size, active drain region overlap of drain contact CC, metal bit line BL overlap of drain contact CC, and metal bit line-to-metal bit line spacing or gap size.
Such ROM cells designed using a 1.0 um design rule range in area from 10 to 15 um.sup.2 and can have densities of up to 2 megabits in dies with reasonable sizes and manufacturing yields. Smaller cell areas and higher cell densities require more aggressive (tighter) design rules, but pushing technology limits generally impairs manufacturing yields. Reducing contact size increases the likelihood that contact windows through passivation will be blocked. Even the open windows' steep side steps are generally poorly covered by deposited metal (as shown in FIGS. 2A and 2B). Strained metal coverage reduces contact reliability. Metal layers for bit lines are harder to define than other layers of semiconductor devices because passivation surface topologies and metal surfaces are rough, and metal films are strongly reflective in the metal masking step. Narrow metal-to-metal spacings facilitate metal-to-metal bit line bridging. Close active region contact-to-gate spacing, and possible misalignment and/or over-etching of non self-aligned drain contact windows, may cause bit lines to short to word lines. Small metal overlap of drain contacts, if part of the contact interface area is exposed during plasma metal etching, may permit trenches in the substrate silicon. Small active drain region overlaps of drain contacts may cause drain junction leakage currents, which can result in logic operation errors. Reducing aluminum contact size may increase Al contact-Si substrate interface resistance.
FIGS. 3A and 3B show a through-hole programming ROM cell described by Masuoka on pp. 146-147 of the Digest of the Integrated Solid State Circuit Conference (ISSCC) 1984. Fabrication of such a cell would need one extra mask for windows to expose the substrate for formation of non-self-aligned buried contacts 100, and a second extra mask for patterning the pad (second) polysilicon layer 102. Metal (Al) contacts 104 are formed on the polysilicon pads 102, which are electrically isolated from the gate (first) polysilicon 106. As long as metal contacts 104 remain within pad polysilicon 102, the metal bit lines 108 will not short to the gates 106, which eliminates the requirement of minimum spacing between the metal contacts and gates and allows reducing the cell size. However, minimum spacings must still be maintained to prevent short circuits between the non-self-aligned buried contacts 100 and gates 106. The size of such a through-hole programming type ROM cell is actually larger than a conventional implant programming type ROM because through-hole programming at the contact mask prevents adjacent cells from sharing drain contact/diffusions, which would short together the adjacent cells. Non-sharable drain contact/diffusion design rules require minimum spacings between drain diffusions and between polysilicon pads for adjacent cells.
Other approaches to scaling down sizes of transistor or memory cells are described for MOS devices in U.S. Pat. No. 4,707,457 entitled "Method For Making Improved Contact For Integrated Circuit Structure" by Erb, and for bipolar devices in U.S. Pat. No. 4,586,968 entitled "Process Of Manufacturing A High Frequency Bipolar Transistor Utilizing Doped Silicide With Self-Aligned Masking" by Coello-Vera. These two processes use oxide deposition and etch-back to form self-aligned buried contacts under individual polysilicon pads.
As shown in FIG. 4A, Erb uses a silicon substrate 20, gate oxide 22, polysilicon gate 24 capped with thick (around 6000 angstrom) oxide layer 28, lightly N-doped (LDD) source/drain region 52, and (2000 to 3000 angstrom) oxide layer 60. As shown in FIG. 4B, Erb applies a contact mask 66 of photoresist aligned over polysilicon gates 24 and over oxide layer 60. Since there are as yet no heavy N++ dopants in the source (or drain) regions, all of the source (and drain) regions need to be exposed after the oxide etching process. Oxide 60 is anisotropically etched to open windows 68 exposing surfaces of LDD regions 52 while preserving oxide spacers 62 adjacent the sidewalls of polysilicon gates 24 to provide insulation later needed between gates 24 and poly contacts 74.
As shown in FIG. 4C, a second polysilicon layer 70 is deposited in and over openings 68. Each source and drain region surface having a self-aligned contact opening 68 forbids continuous polysilicon between source and drain regions, which would be short-circuited. Each source and drain contact opening 68 should be occupied by a ("winged") polysilicon pad, without which the vacant contact openings 68 would be deeply trenched during plasma etching of the winged pad polysilicon. Deep trenches pose a metal step coverage problem and result in high diffusion region-to-contact resistance. Polysilicon layer 70 is heavily doped with N-type dopants which diffuse out through LDD regions 52 to lower the resistance of N+ contacts 54. Polysilicon 70 is masked and patterned to form individual polysilicon contacts 74 with winged pads 76.
Over polysilicon pad contacts 74 is formed an oxide layer 80 through which vias 86 are cut to selected pads 74 and filled with metal 90 to connect the selected pads 74. Finally, metal layer 90 is patterned into bit lines 92 as shown in FIG. 4D.
FIG. 5 illustrates a comparable ROM cell layout with winged polysilicon pads 76 over the areas of the shared drain N+ regions 52=CD forming self-aligned contacts, and with an overlying metal contact bit line 92=BL. Over the source CS1 and CS2 polysilicon pads 76, oxide 80 has no via openings for metal contacts 90, which would short source regions CS through the bit line BL to the drain region CD of each cell.
Scaling down ROM cell sizes by either of these prior art approaches of using self-aligned buried contacts and winged polysilicon pads would have the following drawbacks:
1. FIG. 4B photoresist mask 66 lines must be at least as narrow as the length of the gates (i.e., the width of the word lines) 24 to tolerate possible misalignments while insuring sufficient size openings 68 and insuring adequately consistent thickness oxide sidewall spacers 62. Then, photoresist mask 66 does not effectively protect oxide 60 or oxide sidewall spacers 62 on gate 24. Erb omitting photoresist mask 66 would be equivalent to Coello-Vera.
2. The winged polysilicon pads 74 are heavily doped to lower the resistance of the contacted source and drain diffusion regions 54, but the pads' heavy (N+) dopants diffuse quickly into the substrate 20 and may result in drain diffusion-to-drain diffusion "punch-through". The X dimension of the cell size (drain-to-drain spacing) must be large enough, or increased, to avoid punch-through.
3. Similarly, heavy N+ doping diffusion out from the polysilicon pads may cause objectionable short channel effects such as source/drain punch-through, which must be forestalled by lengthening the channel, which increases the Y dimension of the cell size.
4. The polysilicon bit line cannot be replaced by polycide film to lower the bit line resistance because silicide film is susceptible to peeling by the concentrated N+ dopants used in the winged polysilicon contacts to dope the source/drain regions.
5. As with conventional buried polysilicon contacts, undersized (smaller than the defined polysilicon pattern) buried polysilicon contacts in peripheral circuits are impractical due to the very high resistance of the N- active regions 52. This restricts and may enlarge ROM cell layouts.
6. Metal bit lines are needed in ROM memory cells to electrically connect the individual winged pad polysilicon contacts 74 of the drain N+ diffusions 54. Any non-opened windows for metal contacts will incapacitate the corresponding cells, and metal bit lines are plagued by bridging between bit lines.
7. Cell design rules would be enlarged in both the X and Y dimensions to guarantee sufficient overlaps between the underlying winged polysilicon pad and metal contacts and between the metal contacts and the overlying metal of the bit lines.
8. Critical dimensions of the gate, metal (or even polysilicon) step coverage, and word line-to-word line spacing when the gates are covered by a very thick (6000 angstrom) layer of oxide may require increasing the Y dimension of the cell size.
Thus, conventional metal bit line cell structures are not small enough to build very high density memory arrays without sacrificing production yields. There is a need for an improved and more reliable technique of fabricating semiconductor device cells small enough for ultra-high (4 to 16 megabit) density memory array products.